Πλοήγηση ανά Θέμα "VLSI circuits"
Αποτελέσματα 1-17 από 17
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Asynchronous sub-threshold ultra-low power processor
(2015)Ultra low power VLSI circuits may enable applications such as medical implants, sensor networks and things for IoT. Aggressive supply voltage scaling is known to significantly improve power consumption and efficiency, but ... -
Exploration of 2D cellular automata as binary sequence generators
(2010)In this work a comprehensive exploration of Binary Sequence Generators (BSG) is offered, focusing on an alternative type of BSG (radix-2 counter) presenting low design complexity and interesting speed characteristics, based ... -
Hardware Trojan Classification at Gate-level Netlists based on Area and Power Machine Learning Analysis
(2021)The 21st century has been characterized by incredible technological advancements. A key factor of this revolution is the ever-growing circuits complexity that are the core components of all electronic devices. This revolution ... -
Investigation and trade-offs in 3DIC partitioning methodologies: N/A
(2019)In this work, we compare alternative 3DIC partitioning methodologies, in terms of slack, number of inter-tier vias, Tier Area Ratio (TAR) and HPWL design parameters. The popular 3DIC postplacement, bin-based Fidducia-Mattheyses ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ... -
A low-power CMOS VLSI circuit for signal conditioning in integrated capacitive sensors
(2004)Capacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire ... -
A low-power VLSI architecture for intra and inter prediction in H.264
(2006)The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The keys to this high code efficiency are mainly the two prediction modes (Intra & Inter) provided by the standard. ... -
Merging R-trees
(2004)R-trees, since their introduction in 1984, have been proven to be one of the most well-behaved practical data structures for accommodating dynamic massive sets of geometric objects and conducting a diverse set of queries ... -
Metal stack and partitioning exploration for monolithic 3D ICs
(2020)In this work, we investigate the effect of metal stack and tier 3D IC partitioning methodologies on the Quality of Results (QoR) of monolithic 3D circuits compared to their 2D counterparts. Two interconnect options are ... -
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
(2019)A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient ... -
R-Abax: A radiation hardening legalisation algorithm satisfying TMR spacing constraints
(2020)Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient ... -
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL
(2020)Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening ... -
Scavenging PyPi for VLSI Packages
(2022)Application Specific Integrated Circuits and Field Programmable Gate Arrays as well as their respective design flows have been the focus of many studies. As such the use of EDA tools becomes a necessity while researchers ... -
A SoC-ZYNQ-Based SW-HW Co-Simulation and Verification Method
(2019)An architecture enabling a flexible on-board simulation and verification method for complex user-specific IPs is presented. The proposed method relies on an FPGA-SoC implementation of a golden simulation and verification ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ... -
STA for mixed cyclic, acyclic circuits
(2020)In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ... -
Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits
(2021)A statistical approach for the estimation of maximum and minimum leakage power in CMOS Very Large Scale Integration (VLSI) circuits is proposed in this paper. The approach is based on the discipline of statistics known as ...